RFEL signal processing iq : fpga expertise


Video Processing

IP Cores

Digital Stabilisation

RFEL's Digital Stabilision IP core eliminates unwanted camera shake and produces an output that appears to have come from a stable platform. It is a highly optimised, best-in-class video processing solution. Incorporate this cutting edge capability into your vision application to add significant competitive advantage to your product, whilst simultaneously reducing risk and time-to market.

Digital Stabilisation is a real-time global movement correction processing module which is designed to meet the most demanding requirements of rugged driver assistance systems, but can be easily tailored to different applications, like pole mounted devices and sighting devices, using the comprehensive range of run-time control parameters.


  • Stabilisation for daylight, Infrared (IR), and fused video streams
  • Real-time, low-latency
  • Up to 150 fps, up to 1080p, depending on target device and resources
  • Stabilisation accuracy performance of the total frame-to-frame movement is equivalent to ±1% of the vertical field of view (VFOV) of the camera
  • Stabilisation for camera movements in x and y directions (translation) and rolling (either centred within or outside of the image frame)
  • Recovery from irregular, single, movements of ± 15% of the VFOV within 0.1 seconds of the event
  • Full, run-time parametric control of local and global scene movement response characteristics
  • Panning filter control

Add competitive advantage to surveillance and situational awareness applications which are subject to small and large movements of the camera or sensor platform. Digital Stabilisation is especially effective for long range surveillance applications where users benefit from improved detection, recognition and identification performance; in addition to reduced viewer fatigue and reduced false positives.

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Digital Stabilisation Block Diagram



Input Motion Estimation Robust to defocus, strong local movement, low light and scenes sparse in features
Output Image Correction Real-time, low latency, removal of unwated global movement
Horizontal Correction +/- ~ 50 pixels (1)
Vertical Correction +/- ~ 50 pixels (1)
Rotational Correction +/- 5 to 10 degrees (1)



1080p to be certified soon

Frame Rates Up to 60fps
Latency < 2 frames, optimised to function
Temporal Cut-off Frequency for Stabilisation User definable, but typically >0.5Hz
Adaptive Panning Control Confidential: contact RFEL for details
Rolling shutter Robust to the effects of rolling shuttier in the unput image (2)
Supported Devices

Xilinx Zynq TM - 700 / Artix TM - 7 / Kintext TM - 7

Altera Arria ® - V SoC to be certified soon

Delivery Scripts, documents and simulation libraries

(1) Depending on the statistics of scene movement
(2) Does not correct for rolling shutter

Platform Support

  • Altera
  • Xilinx
  • Xilinx Zynq

RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application.
For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides design services to help with the process of integration.

Along with the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for simulation and synthesis.

Supplied Item


Design Netlist
Constraints File Vendor-Specific
Instantiation Template VHDL
Verification VHDL test bench including Modelism script and test data files

Compiled RTL VHDL model

Bit-true MATLAB model and scripts

Implementation reports

Software Linux shared object library

Ordering Information


Part Number

DS Xilinx Zynq ® - 7020 IP10-04-ZA
DS Xilinz Zynq ® - 7030/45 IP10-04-ZK
DS Xilinx Artix ® - 7 IP10-04-A7
DS Xilinx Kintex® - 7 IP10-04-K7
Altera ArriaV SoC 5ASXB3 Contact RFEL sales

For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

Depending on configuration, DS requires a frame buffer memory; all interfaces (video, memory and control) are implemented as flexible AXI compliant interfaces or similar. As for all RFEL IP cores, DS is backed up by a detailed bit-true MATLABTM model of the processing. Contact RFEL for options to evaluate performance with suitable sample video sequences.

Example Resource Usage

 FPGA Family

FPGA Part Number

Xilinx Zynq-7020


Registers 17966 / 17%
LUTs 16425 / 31%
Block RAMs 87 / 62%
DSP48Es 110 / 50%

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