RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Fourier Analysis

OctoSpeed

RFEL’s OctoSpeed FFT cores process complex input data in continuous real time, with no gaps in the data and at complex data rates to 1.6 Gsps. They are highly optimised in terms of their memory, multiplier and logic use.

Features

  • Continuous real-time processing of complex data in excess of 1.6 Gsps
  • Optimised for the speed silicon trade-off
  • Optional Input Buffer and Bit Reverser
  • Continuous real-time processing compatible with >3 Gsps ADC using RFEL’s optional DHBF
  • 16 to 128K-point versions available (longer lengths by request)
  • Bit-width and bit-growth adjustable 
  • Twiddle-width adjustable 
  • Can be used for real input FFTs with additional modules
  • Targeted at Xilinx and Altera FPGA families

Please enter the word you see in the image below:


OctoSpeed FFT Block Diagram

Parameter

Specification

Input Data Rate To ~1.6 Gsps
Input Type 1x Complex
Input Interleaving None
Input Buffer Optional, including optional reorder
Input Window Optional
Internal Parallelism 4x Complex
FFT Length 16 to 128k-pt (longer on request)
FFT Mode FFT or Inverse FFT (build or run-time configurations
Length Adaptations Switchable (optional run-time back-to-back switching)
Output Order Scrambled or reordered to natural

Platform Support

  • Altera
  • Xilinx

Customisation
RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides design services to help with the process of integration.

Deliverables
In addition to the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for simulation and synthesis.

Supplied Item

Description

Design

Netlist

Constraints File

Vendor Specific

Instantiation Template

VHDL

Verification

VHDL test bench including Modelsim script and test data files.

Compiled RTL VHDL model.

Bit-true Matlab model and scripts.

Implementation reports.

Warranty
For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

Support
RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support packages that can be booked separately.

The following implementation figures are for the following OctoSpeed FFT configuration:

  • 4k-point transform
  • 12-bit in
  • 24-bit out
  • 18-bit twiddles.

FPGA Family

Xilinx Virtex 7

Altera Stratix 5

FPGA Part No

XC7V585T-1FFG1157

5SGSEB7I2F40C2

Registers

12789

9486

LUTs

6784

7148

18Kb Block RAMs

14

-

36Kb Block RAMs

38

-

M20K RAMs

-

74

DSP48Es

60

-

DSP Blocks

-

51

FMax

>350MHz

>250MHz

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