RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Fourier Analysis


HyperSpeed is an exceptionally fast FFT core. It is ideal for applications where both high processing speed and efficient FPGA resource usage are critical. Using an advanced parallel pipelined architecture, HyperSpeed can process data continuously in real time at rates of over 100 Gsps. Its highly configurable design features scalable transform length and processing parallelism and can be tailored to any one of a huge field of applications. HyperSpeed offers both the flexibility and performance demanded for a new generation of high performance signal processing tasks.


  • A fixed sample rate of between 3.6 Gsps and over 52 Gsps for real-valued data (equivalent to between 1.8 Gsps and 26 Gsps for complex data)
  • Complex parallelisms of between 4 and 256 (factory setting)
  • Dynamic selection of FFT or IFFT transform
  • Continuous real-time data processing at > 100 Gsps
  • A wide range of choices for processing parallelism, selected at build-time
  • FFT length up to 128k-points, with larger transforms available subject to parallelism and FPGA resource requirements
  • Factory-adjustable precision and scaling
  • Flexibility in balancing usage of different FPGA resources
  • A choise of data format and ordering options

Please enter the word you see in the image below:

HyperSpeed FFT Block Diagram



Input Data Rate To ~100 Gsps
Input Type 1x Complex
Input Interleaving None
Input Buffer Optional, including optional reorder (build option)
Input Window Optional, including user defined type
Internal Parallelism Flexible, defined at build time, sample rate dependent
FFT Length 32 to 128k-pt
FFT Mode FFT or Inverse FFT (build or run-time configurations
Length Adaptation Switchable (optional run-time back-to-back switching)
Output Order Scrambled or reordered to natural

Platform Support

  • Altera
  • Xilinx

RFEL offers a range of options and additional IP blocks which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides Design-IQTM design services to help with the process of integration.

Supplied Item




Constraints File

Vendor Specific

Instantiation Template



VHDL test bench including Modelsim script and test data files

Compiled RTL VHDL model

Bit-true Matlab model and scripts

Implementation reports

For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support pacakages that can be booked separately.

The following implementation figures are for the following HyperSpeed configuration:

  • 1k point transform
  • 64 inputs
  • 12-bit in
  • 22-bit out
  • 18-bit twiddles
  • 16GS/s aggregate input data rate

FPGA Family

Xilinx Virtex 7 Altera Stratix 5

FPGA Part Number

XC7V585T-2FFG1157 5SGSEB8I2F45C2





54071 71664

Block RAMs

48 -

36kb Block RAMs

286 -


- 341


720 -

DSP Blocks

- 596


>250MHz >250MHz

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