RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Channelisers and Down-Converters

Wideband DDC

The flexible Wideband Digital Down Converter IP core, for ultra-high speed, high bandwidth, signal processing applications, has been produced to accept a single input channel (multiple channels available on request) sampled at a rate as high as 3.6 Gsps. Wideband DDC produces a down converted channel with decimated output sample rate, selectable within the range 1 Ksps to 225 Msps. This wideband capability is complimented by the flexibility of being able to specify the mix frequency and output sample rate with a precision of 1 Sps.

Wideband DDC Tower Image


  • Input sample rate up to 3.6 Gsps
  • Signal bandwidth of up to 180 MHz extractable from entire input bandwidth
  • High performance filtering: spurious free dynamic range (SFDR) of at least 80 dB
  • Peak-to-peak passband ripple of less than 0.1 dB
  • Mix frequency and output sample rate specified to a resolution of 1 Hz
  • Targets the latest FPGA technology
  • Easily configurable to the customer's specific needs

The ability to coherently down convert a signal, with a bandwidth as high as 180 MHz, from within input band 1.8 GHz, makes Wideband DDC an obvious choice for communications, electronic warfare and surveillance applications..
Wideband DDC uses an efficient and high performance architecture that exploits the latest advances in FPGA technology. The ability to specify the mix frequency and output sample rate to a precision of 1 Sps over such large ranges makes the flexible Wideband DDC highly amenable to simple system integration.

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Wideband DDC Architecture Block Diagram



Number of Inputs Single real input (additional coherent or incoherent input channels available upon request)
Input Sample Rate Up to 3.6 Gsps
Input Resolution 12-bit signed 2's complement
Number of Independent DDCs

Single complex output (additional coherent or incoherent output channels available upon request)

Tuning Range

Over complete range of input bandwidth, within limits imposed by signal bandwidth
Tuning Resolution Steps of 1 Hz over the whole tuning range
Output Sample Rate Can be specified in the range 1 Ksps (typ. audio) to 225 Msps in steps of 1 Sps
Output Bandwidth Alias-free bandwidth guaranteed to be at least 80% of output sample rate (800 Hz to 180 MHz)

80 dB.

Defines stopband attenuation and maximum permissible spur level

Passband Ripple

≤0.1 dB pk-pk

Output Bit-width

24-bit signed 2's complement I&Q
Parameters can be adjusted at build-time on request, to suit requirements.

Platform Support

  • Altera
  • Xilinx

RFEL offers a range of options and additional IP blocks, which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides Design-IQTM FPGA design services to help with the process of integration.

Supplied Item


Design Netlist
Constraints File Vendor Specific
Instantiation Template VHDL

VHDL test bench including Modelism script and test data files

Compiled RTL VHDL model

Bit-true Matlab model and scripts

Implementation reports

Design Netlist

Ordering Information


Part Number

Wideband DDC Xilinx Kintex® - 7

​IP 01-04-K7

Wideband DDC Xilinx Virtex® - 7

IP 01-04-V7

Wideband DDC Xilinx Virtex® - 6

IP 01-04-V6

Wideband DDC Xilinx Virtex® - 5

IP 01-04-V5

Wideband DDC Altera Stratix® - V

Contact RFEL sales

For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support packages that can be booked separately.

Example resource usage on Xilinx Kintex XC7K70T

Resource type



19426 / 24%


12238 / 30%

36kb Block RAM

19 / 14%


106 / 44%

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