RFEL signal processing iq : fpga expertise

Signal Processing

IP Cores

Channelisers and Down-Converters

ChannelCore Flex

ChannelCore Flex redefines the limits of channeliser technology. It outperforms existing digital down-converter (DDC) ASICs and FPGA cores and can be fully tailored to the needs of an individual application. ChannelCore Flex is unique in supporting thousands of channels, each with independent bandwidth and tuning controls that can be changed even during operation. Thanks to advanced algorithms and a highly optimised implementation, this combination of flexibility and performance is achieved with extremely efficient use of FPGA resources. 

ChannelCore Flex Display


  • Thousands of channels on any bandwidth
  • Dynamic independent control of the gain, centre frequency, bandwidth, sample rate and filter response of each channel
  • Over 80 dB spurious free dynamic range
  • Up to 4 inputs 
  • Support for several thousand independently defined channels
  • Channel parameters that can be specified to an accuracy of better than 0.06 Hz
  • Dynamic reprogramming of channels without disturbing the operation of other channels
  • High aggregate sample rates of desired channels compared to rival channelisers
  • Support for a range of input formats and sample rates
  • Typical complex input sample rates of 500 Msps in mid-range FPGAs, with rates over 1 Gsps for certain channel plans in high-end devices
  • Eight 64-tap low-pass (shaping) filters with more or longer filters
  • Control of individual channel gain over a dynamic range of 90 to 102.3 dB in 0.1 dB steps
  • Global frequency offsets that can be independently applied to the inputs


  • Software-defined/cognitive radio
  • Electronic warfare
  • Broad-spectrum surveillance
  • Communications profiling
  • Providing a direct feed to a multi-channel satellite demodulator
  • Instrumentation and measurement
  • Scientific applications

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Platform Support

  • Xilinx

RFEL offers a range of options and additional IP blocks, which allow this product to be delivered in the configuration best suited to the precise needs of a particular application. For more demanding requirements, deeper systems integration, or in cases where further customisation is required, RFEL also provides design services to help with the process of integration.

In addition to the netlist for each IP core, RFEL supplies a comprehensive set of models, scripts and test benches for simulation and synthesis.

Supplied Item




Constraints File

Vendor Specific

Instantiation Template



VHDL test bench including Modelsim script and test data files.

Compiled RTL VHDL model.

Bit-true Matlab model and scripts.

Implementation reports.



Ordering Information


Part Number

Standard Version


Wideband Version


For peace of mind RFEL provides a twelve month warranty as standard. If required, this can be extended as part of a contract at a reasonable extra cost.

RFEL understands that customers might need some support in integrating the IP cores into their systems, and so offers support packages that can be booked separately.



Number of Input Channels 1
Number of Independent Output Channels 256
Rate Conversion Integer Up-sample Range

216 ≤ L ≤ 227

Rate Conversion Integer Down-sample Range

230 ≤ M ≤ 231

Minimum Output Channel Sample Rate fin x Lmin / Mmax = fin / 32768
No. of Programmable Output Filter Taps 31
No. of Programmable Output Filter Coefficient Sets 32
Target FPGA Xilinx Kintex-7: XC7K410T-1
- Utilisation (6-ip LUTs) 22% (56,000)
- Utilisation (fabric registers) 15% (73,000)
- Utilisation (DSP48E) 32% (492)
- Utilisation (36kb BRAMs) 36% (284)

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